1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method of fabricating the same and, more particularly, to a structure of a semiconductor substrate connected to an external leadwire, and a method of fabricating that structure.
2. Description of the Related Art
In connecting a semiconductor integrated circuit (IC) device, such as IC or LSI circuit, to an external circuit, a bonding pad on a chip comprising a semiconductor substrate is connected to external lead wires on a package by Au or Al wires. FIG. 1A shows a conventional structure of a bonding pad portion (electrode leading portion) provided to electrically connect a lead wire of the package to an internal circuit of the chip. In FIG. 1A, an insulating film 4 made of BPSG or the like is formed on a semiconductor substrate 1 to cover the gate electrode, etc. Formed on the insulating film 4 is an Al wiring 12 consisting of Al, Si, Cu, etc., which is lead out from the internal circuit. This is where a lead wire 14 is connected, and thus serves as a bonding pad portion 30. The wiring 12 including this bonding portion is covered with a top passivation film 13. To improve the reliability of the Al wiring, a barrier metal structure having, for example, an Al--Si--Cu film 12, a TiN film 11 and Ti film 10 laminated has recently been used as a wiring material, as shown in FIG. 1B. Accordingly, boron in a BPSG film normally used as the insulating film 4 and the Ti film 10, the lowest portion of the laminated wiring, produce a reaction product TiBx. Since this product is chemically stable, the Ti film 10 is shorn from the BPSG film 4 when tensile stress is externally applied via the lead wire 14 to the bonding pad portion. As the boron concentration in the BPSG film gets higher (approximately 1.times.10.sup.21 P/cm.sup.3 or above), this phenomenon becomes more prominent.
To prevent such film shearing, the use of the structure as shown in FIG. 2D has been proposed. That is, a pad bed layer 5 is provided between the BPSG insulating film 4 in the bonding pad region and the laminated wiring (Al--Si--Cu/TiN/Ti) to prevent the BPSG film 4 from directly contacting Ti in the laminated wiring. In view of the adhesion between the BPSG film 4 and Ti, the pad bed layer 5 is formed of a high melting-point metal which does not easily react with polycrystalline silicon (hereinafter simply referred to as "polysilicon") or boron, or its silicide or the like.
The fabrication processes of this prior art will be described referring to FIGS. 2A to 2D. As shown in FIG. 2A, a polysilicon gate 2 and a diffusion region 3 are provided in the left-half device region of the semiconductor substrate 1 to form a transistor or another device. The BPSG insulating film 4 is deposited as an insulating film on the surface of the resultant structure. Then polysilicon is deposited as the pad bed layer 5 on the entire surface of the resultant structure. As shown in FIG. 2B, a resist pattern (not shown) is formed using photolithography to leave the pad bed layer 5 of polysilicon in the region where a bonding pad is to be formed later. Then, part of the diffusion region 3 in the semiconductor substrate 1 is exposed to form a contact hole 6 in the BPSG insulating film 4, as shown in FIG. 2B. Subsequently, as shown in FIG. 2C, the Ti film 10, TiN film 11 and Al--Si--Cu film 12 are sequentially deposited by a sputtering method. After the laminated wiring consisting of the Ti film 10, TiN film 11 and Al--Si--Cu film 12 is processed according to a wiring pattern, a top passivation film 13 is deposited on the entire surface of the resultant structure. Then, the top passivation film 13 is etched according to a resist pattern to form a bonding pad portion, as shown in FIG. 2D. Then, the lead wire 14 is bonded on the wiring of a pad opening portion 30 to provide electric connection to an external circuit. As the BPSG film 4 cannot directly contact the Ti film 10 of the laminated wiring at the bonding pad portion in this example, film shearing can be prevented but with an increased process for depositing and processing the pad bed layer 5.
A multi-layered wiring structure becomes popular to cope with recent miniaturization of a semiconductor IC device such as LSI. In this structure, an upper wiring is deposited through an interlayer insulating film on the wiring on the semiconductor substrate. The upper and lower wirings are electrically connected by a low-resistance material buried in a contact hole formed in this interlayer insulating film. This involves an additional technology of burying a low-resistance material in the contact hole, increasing the fabrication processes.
FIGS. 3A and 3B illustrate cross sections in the processes of burying tungsten (W), for example, in the contact hole. The fabrication up to the formation of the contact hole 6 is the same as in FIG. 2B. FIG. 3A shows a cross section after selectively growing a tungsten (W) layer 23 after the formation of the contact hole 6. While the W layer 23 is selectively formed on the contact portion, it also selectively grows on the pad bed layer 5. The bonding pad formed in this manner cannot keep sufficient strength against the tensile stress that is externally applied via the lead wire. FIG. 3B shows a cross section after depositing the W layer 23 on the entire surface by a blanket method. In this case, since the pad bed layer 5 is formed of a polysilicon film, a layer of a high melting-point metal or its silicide, a sufficient selection ratio to W may not be secured so that the layer 5 may be also be etched at the time W is etched back. As a solution to this problem, the pad bed region may be masked with a resist pattern at the time W is etched back. This method yields a bonding pad having a laminated structure of pad bed material and contact-hole burying tungsten. But, this structure cannot keep sufficient strength against the tensile stress that is externally applied via the lead wire. It is also know to use polysilicon as the contact-hole burying material. The main flow of the process of burying polysilicon in the contact hole is to perform the etch-back step after depositing polysilicon on the entire surface of the resultant structure. This is substantially the same as the case where W is formed by the blanket method. As polysilicon has a high resistivity, it is doped with an impurity to serve as the contact-hole burying material. In the case where boron is used as an impurity, if the polysilicon film is left on the bonding pad portion, it produces TiBx together with Ti deposited on that polysilicon film, lowering the adhesion, as mentioned earlier. If the polysilicon film is to be removed at the time the etch-back step is carried out, a sufficient etching ratio to the pad bed material cannot be secured, as discussed earlier.
In short, as the miniaturization of semiconductor IC devices progresses, a step of burying a low-resistance material (contact plug) for connection between wirings or a wiring and the device region should be performed in addition to a step of forming the pad bed, thus increasing the number of steps. If a new material is selected for the pad bed, when it adapts poorly to the underlying insulating film containing boron such as BPSG, this pad bed will be shorn from the insulating film by the tensile stress applied via the lead wire. Further, in the case where a plug is formed in the contact hole, when an extra plug forming material formed on the semiconductor substrate is etched out, the necessary pad bed is etched out at the same time, as described above.